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NXP Semiconductors /LPC18xx /CGU /PLL0AUDIO_MDIV

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Interpret as PLL0AUDIO_MDIV

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0MDEC0RESERVED

Description

PLL0AUDIO M-divider register

Fields

MDEC

Decoded M-divider coefficient value. Select values for the M-divider between 1 and 131071.
RESERVED

Reserved

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data